1. Technical Field
The present disclosure generally relates to a memory circuit, and more particularly to a data outputting method of a memory circuit, the memory circuit, and a layout of the memory circuit.
2. Description of Related Art
Flash memories are used in a variety of applications in electronics. These memory circuits often include a large number of input and output pins to accommodate data and addresses required to access the memory cells. In response to increasing space and wiring demands, serial flash memories have been developed to provide reduced pin counts, often requiring only one or two data pins. These serial flash memories provide a storage solution for systems with limited space, pin connections, and power supplies. Serial flash memories can be used for code download applications, as well as for storage of voice, video, text, and data, etc. However, conventional serial flash memory circuits have many limitations. For example, a conventional serial peripheral interface flash memory circuit transfers data or address bits in a sequential and serial fashion, increasing the design complexity and layout area of the memory circuit.
Referring to FIG. 1A, FIG. 1A is a wave diagram showing outputs of a serial peripheral interface memory circuit. The serial peripheral interface memory circuit is provided by U.S. Pat. No. 7,613,049, and a dual data outputting method is proposed and applied therein. The memory circuit includes a clock signal, a plurality of pins, and a configuration register. The configuration register includes a wait cycle count.
The dual data outputting method uses a first input/output pin SI/SIO0 and a second input/output pin SO/SIO1 to concurrently transmit a read address to the memory circuit, wherein the read address includes at least a first address bit and a second address bit, the first address bit is transmitted via the first input/output pin SI/SIO0, and the second address bit is transmitted via using the second input/output pin SO/SIO1. The first address bit for example is one of address bits A22, A20, . . . , A2, and A0. The second address bit for example is one of address bits A23, A21, . . . , A3, and A1.
The dual data outputting method accesses the memory circuit for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The dual data outputting method transfers batches of data from the memory circuit by using the first input/output pin SI/SIO0 and the second input/output pin SO/SIO0 concurrently. To put it concretely, the first input/output pin SI/SIO0 sequentially outputs the 7 batches of the data D6, D4, D2, D0, D6, D4, D2 at the 7 falling edges of the 27th through 33th clocks of the clock signal SCLK, and the second input/output pin SO/SIO1 sequentially outputs the 7 batches of the data D7, D5, D3, D1, D7, D5, D3 at the 7 falling edges of the 27th through 33th clocks of the clock signal SCLK.
Referring to FIG. 1B, FIG. 1B is a wave diagram showing outputs of a serial peripheral interface memory circuit. The serial peripheral interface memory circuit is also provided by U.S. Pat. No. 7,613,049, and a quadruple data outputting method is proposed and applied therein. The memory circuit includes a clock signal, a plurality of pins, and a configuration register. The configuration register includes a wait cycle count. It is noted that the memory circuit herein is the same as the memory circuit corresponding to FIG. 1A, and either quadruple or dual data outputting method can be applied in the memory circuit.
The quadruple data outputting method uses a first input/output pin SI/SIO0, a second input/output pin SO/SIO1, a first control input/output pin WP#/SIO2, and a second control input/output pin HOLD#/SIO3 to concurrently transmit a read address to the memory circuit, wherein the read address includes at least a first address bit, a second address bit, at least a third address bit, and at least a fourth address bit. The first address bit is transmitted via the first input/output pin SI/SIO0, the second address bit is transmitted via using the second input/output pin SO/SIO1, the third address bit is transmitted via using the first control input/output pin WP#/SIO2, and the fourth address bit is transmitted via using the second control input/output pin HOLD#/SIO3. The first address bit for example is one of address bits A20, A16, . . . , A4, and A0. The second address bit for example is one of address bits A21, A17, . . . , A5, and A1. The third address bit for example is one of address bits A22, A18, . . . , A6, and A2. The fourth address bit for example is one of address bits A23, A19, . . . , A7, and A3.
The quadruple data outputting method accesses the memory circuit for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The quadruple data outputting method transfers the batches of the data from the memory circuit by using the first input/output pin SI/SIO0, the second input/output pin SO/SIO1, the first control input/output pin WP#/SIO2, and the second control input/output pin HOLD#/SIO3 concurrently. To put it concretely, the first input/output pin SI/SIO0 sequentially outputs the 7 batches the data D4, D0, D4, D0, D4, D0, D4 at the 7 falling edges of the 21th through 27th clocks of the clock signal SCLK, the second input/output pin SO/SIO1 sequentially outputs the 7 batches of the data D5, D1, D5, D1, D5, D1, D5 at the 7 falling edges of the 21th through 27th clocks of the clock signal SCLK, the first control input/output pin WP#/SIO2 sequentially outputs the 7 batches of the data D6, D2, D6, D2, D6, D2, D6 at the 7 falling edges of the 21th through 27th clocks of the clock signal SCLK, and the second control input/output pin HOLD#/SIO3 sequentially outputs the 7 batches of the data D7, D3, D7, D3, D7, D3, D7 at the 7 falling edges of the 21th through 27th clocks of the clock signal SCLK.
Referring to FIG. 2A, FIG. 2A is a schematic diagram showing a layout of the memory circuit using the dual data outputting method. The memory circuit has 16 data buffers DQ[0]˜DQ[15], and a first input/output pin, a second input/output pin, a first control input/output pin, and a second control input/output pin are respectively connected to data buffers DQ[0]˜DQ[3], so as to output the 4 batches of the data stored in the data buffers DQ[0]˜DQ[3].
A metal line is connected between the data buffers DQ[2k] and DQ[2k+2], so as to transfer the batch of the data stored in the data buffer DQ[2k+2] to be stored in the data buffer DQ[2k] when the data buffers DQ[2k] and DQ[2k+2] are triggered by the clock signal, wherein k is an integer from 0 through 2. Furthermore, a metal line is connected between the data buffers DQ[2k+1] and DQ[2k+3], so as to transfer the batch the data stored in the data buffer DQ[2k+3] to be stored in the data buffer DQ[2k+1] when the data buffers DQ[2k+1] and DQ[2k+3] are triggered by the clock signal. A metal line is connected between the data buffers DQ[2j] and DQ[2j+2], so as to transfer the batch of the data stored in the data buffer DQ[2j+2] to be stored in the data buffer DQ[2j] when the data buffers DQ[2j] and DQ[2j+2] are triggered by the clock signal, wherein j is an integer from 4 through 6. A metal line is connected between the data buffers DQ[2j+1] and DQ[2j+3], so as to transfer the batch of the data stored in the data buffer DQ[2j+3] to be stored in the data buffer DQ[2j+1] when the data buffers DQ[2j+1] and DQ[2j+3] are triggered by the clock signal.
Both referring to FIG. 1A and FIG. 2A, when the dual data outputting method is applied in the memory circuit, the first control input/output pin WP#/SIO2 and the second control input/output pin HOLD#/SIO3 respectively connected to the data buffers DQ[2] and DQ[3] are forbidden. Before the falling edge of the 27th clock of the clock signal SCLK occurs, the data buffers DQ[0]˜DQ[7] respectively store the 8 batches of the data D6, D7, D4, D5, D2, D3, D0, D1. When the falling edge of the 27th clock of the clock signal SCLK triggers the data buffers DQ[0]˜DQ[7], the 2 batches of the data D6, D7 stored in the data buffers DQ[0], DQ[1] are output respectively via the first input/output pin SI/SIO0 and the second input/output pin SO/SIO1, and the data buffers DQ[0]˜DQ[7] respectively store the 8 batches of the data D4, D5, D2, D3, D0, D1, D6, D7. According to the same manner, the batches of the data stored in the data buffers DQ[0]˜DQ[7] at the falling edges of the 28th through 33th clocks of the clock signal SCLK can be known.
Referring to FIG. 2B, FIG. 2B is a schematic diagram showing a layout of the memory circuit using the quadruple data outputting method. The memory circuit has 16 data buffers DQ[0]˜DQ[15], and a first input/output pin, a second input/output pin, a first control input/output pin, and a second control input/output pin are respectively connected to data buffers DQ[0]˜DQ[3], so as to output the 4 batches of the data stored in the data buffers DQ[0]˜DQ[3].
A metal line is connected between the data buffers DQ[4k] and DQ[4k+4], so as to transfer the batch of the data stored in the data buffer DQ[4k+4] to be stored in the data buffer DQ[4k] when the data buffers DQ[4k] and DQ[4k+4] are triggered by the clock signal, wherein k is an integer from 0 through 2. A metal line is connected between the data buffers DQ[4k+1] and DQ[4k+5], so as to transfer the batch of the data stored in the data buffer DQ[4k+5] to be stored in the data buffer DQ[4k+1] when the data buffers DQ[4k+1] and DQ[4k+5] are triggered by the clock signal. A metal line is connected between the data buffers DQ[4k+2] and DQ[4k+6], so as to transfer the batch of the data stored in the data buffer DQ[4k+6] to be stored in the data buffer DQ[4k+2] when the data buffers DQ[4k+2] and DQ[4k+6] are triggered by the clock signal. A metal line is connected between the data buffers DQ[4k+3] and DQ[4k+7], so as to transfer the batch of the data stored in the data buffer DQ[4k+7] to be stored in the data buffer DQ[4k+3] when the data buffers DQ[4k+3] and DQ[4k+7] are triggered by the clock signal.
Both referring to FIG. 1B and FIG. 2B, before the falling edge of the 27th clock of the clock signal SCLK occurs, the data buffers DQ[0]˜DQ[15] respectively store the 16 batches of the data D4˜D7, D0˜D3, D4˜D7, D0˜D3. When the falling edge of the 21th clock of the clock signal SCLK triggers the data buffers DQ[0]˜DQ[15], the 4 batches of the data D4˜D7 stored in the data buffers DQ[0]˜DQ[3] are output via the first input/output pin SI/SIO0, the second input/output pin SO/SIO1, the first control input/output pin WP#/SIO2, and the second control input/output pin HOLD/SIO3, and the data buffers DQ[0]˜DQ[15] respectively store the 16 batches of the data D0˜D7 and D0˜D7. According to the same manner, the batches of the data stored in the data buffers DQ[0]˜DQ[15] at the falling edges of the 22th through 37th clocks of the clock signal SCLK can be known.
Another dual data outputting method applied in a memory circuit, such as the serial flash memory, is illustrated in the U.S. Publication 20060067123. A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin small-outline integrated circuit (SOIC) package and the 8-contact micro leadframe package (MLP), quad flat no leads (QFN) package, or small and thin-type package without lead (SON package) may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.
To sum up, the conventional memory circuit uses its data buffers DQ[0]˜DQ[3] as the output data buffers. Regarding the dual data outputting method, the batch of the data stored in the data buffer DQ[2n+2] is transferred to be stored in the data buffer DQ[2n], and the batch of the data stored in the data buffer DQ[2n+3] is transferred to be stored in the data buffer DQ[2n+1]. Regarding the quadruple data outputting method, the batch of the data stored in the data buffer DQ[n+4] is transferred to be stored in the data buffer DQ[n]. The metal lines responsible for data transferring corresponding to the dual data outputting method are not the same as those corresponding to the quadruple data outputting method. Therefore, the conventional memory circuit needs another 12-metal-line and multiplexer logic control for implementing both of the dual data outputting method and the quadruple data outputting method.